About Me

With over a decade of experience as an Electrical Engineer and Systems Architect, I specialize in High-Performance Computing (HPC), accelerator design, and distributed networking. My approach focuses on end-to-end system analysis, optimizing the entire data path from physical layer to user applications.

I excel at bridging software and hardware, delivering solutions for low-latency Satellite Communications (SATCOM), architecting 5G network accelerators, and designing robust embedded Linux systems.

Experience

Low-Latency LEO Satellite Communications (2025)

Senior Low-latency SatCom Architect
  • Optimized network throughput and latency for Low Earth Orbit (LEO) satellite constellations.
  • Designed a low-latency FPGA-based packet switching architecture supporting 10 GbE and 100 GbE networking.
  • Conducted end-to-end latency optimization from Ethernet ingress to CPU cache processing, ensuring high-reliability data transmission.

5G Network Acceleration & Architecture (2021-2024)

System Architect and Team Lead
  • Architected a 2x25 GbE traffic processing accelerator and a custom L2 Switch on FPGA for high-bandwidth 5G traffic.
  • Designed the Hardware Abstraction Layer (HAL) for seamless SW-FPGA interaction.
  • Implemented IEEE 1588 (PTP) stacks for precise network synchronization.

Embedded Linux & Distributed Systems (2024)

Senior Software Developer (Consultant)
  • Focused on multi-threaded, fault-tolerant C++20 development for embedded Linux systems on Xilinx ZynqMPSoC.
  • Developed custom kernel drivers for character/MDIO devices and designed complex monitoring systems.

High-Performance Feasibility Assessment

Cryptocurrency Mining Application Feasibility
  • Simulated DDR4 bandwidth efficiency to determine hardware viability.
  • Analyzed SHA2/3 processing latency and resource utilization on FPGAs for large-scale operations.

Technical Competencies

Languages

C++ Rust C Python Go Bash TCL

Embedded Linux

Kernel Driver Dev (PCIe, Char, UIO, IIO, MDIO) Devicetree Embedded Linux

System Software

Efficient Data Structures Cache Efficiency Lock-Free Methods Benchmarking

APIs & RPCs

gRPC REST API WebSocket

Parallel Processing

C++/STL Parallel Goroutines pthreads OpenMP MPI

Low-Level Networking

Ethernet PHY (1-100 GbE) L2 Switching

DevOps

Git GitHub GitLab Bitbucket Jenkins GitHub Actions

Cloud

Docker AWS (EC2, Lambda, API Gateway, ECS, S3, VPC)

Development Methodologies

Agile Scrum Management Sprint Planning Standups Sprint Review

Embedded Linux

Kernel Driver Dev PCIe UIO/IIO DeviceTree Yocto

FPGA & Hardware

RTL (Verilog, VHDL) Xilinx System Generator HLS (C/C++) DSP Modeling & Opt. HW/SW Partitioning Fixed-Point Conversion Simulation & Verification Test Automation Timing Closure PCIe Ethernet JESD204B High-Speed Serial Fronthaul Ethernet Vivado Intel Quartus

Signal Processing

DSP MATLAB Python (SciPy) Algorithm Design Filter Design FFT

Networking

100 GbE gRPC NETCONF/YANG L2 Switching IEEE 1588 PTP

5G

5G Radio Design 3GPP L1 Standards (38.10x, 38.21x) L1 Performance Testing Radio Control (DPD, AGC, PTP 1588) Synchronization MIMO & Beamforming Channelizers & DUC/DDC FFT & Matched Filters L1 MATLAB Modeling

Cloud & DevOps

Docker AWS (EC2, Lambda) GitHub Actions Jenkins